The present invention relates to a method and a system for vector dividing. More particularly, the invention relates to a method and a system for vector dividing employing convergence division.
As is well known, in convergence division, sequential repeated multiplying operations are performed both for a divisor and a dividend, these being multiplied with a plurality of convergence factors employing a recurrence formula to converge the result of the repeated multiplying operation. Specifically, the divisor converges to 1 and the result of the repeated multiplying operation of the dividend converges to the quotient. The result of the division is thereby obtained.
The convergence division will be discussed in further detail by taking an example of N.div.D (0&lt;N&lt;D). In the dividing operation for N.div.D, at first, a sequence P.sub.0, P.sub.1, . . . , P.sub.n-1, with which a product obtained by multiplying the sequence with the divisor D converges to 1, is found. EQU D.times.P.sub.0 .times.P.sub.1 .times. . . . .times.P.sub.n-1 .fwdarw.1
At this time, N.times.P.sub.0 .times.P.sub.1 .times. . . . .times.P.sub.n-1 converges to a quotient Q as expressed in the following formula: ##EQU1##
Assuming that the divisor D has a value in the range of 1/2.ltoreq.D&lt;1, the divisor D can be expressed by the following equation: EQU D=1-.eta.(0&lt;.eta..ltoreq.1/2)
Then, assuming P.sub.0 =1+.eta., the next divisor D.sub.1 can be derived through the following equation: EQU D.times.P.sub.0 =D.sub.1 =1-.eta..sup.2 (0&lt;.eta..sup.2 .ltoreq.2.sup.-2)
Next, assuming P.sub.1 =1+.eta..sup.2, the subsequent divisor D.sub.2 can be derived through the following equation: EQU D.times.P.sub.0 .times.P.sub.1 =D.sub.2 =1-.eta..sup.4 (0&lt;.eta..sup.4 .ltoreq.2.sup.-4)
From the above, the divisor D.sub.i can be generally expressed by the following equation and converges to 1: EQU D.times.P.sub.0 .times.P.sub.1 .times. . . . .times.P.sub.i-1 =D.sub.i =1-.eta..sup.2(i+1)
Since P.sub.0 =1+.eta., D=1-.eta., P.sub.0 +D=2, therefore, the relationship expressed by the following equation can be obtained: EQU P.sub.0 =2-D, P.sub.1 =2-D.sub.1, . . . P.sub.i =2-D.sub.i . . .
Accordingly, respective values of P.sub.i can be obtained by deriving the two's complement of D.sub.i. Then, as set forth above, N.times.P.sub.0 .times.P.sub.1 .times. . . . .times.P.sub.n-1 can converge to the quotient Q. Therefore, the quotient Q can be obtained through the following operation. ##EQU2##
As set forth above, in the convergence division described, a plurality of multiplying operations as expressed by the equations (1) through (2n-1) has to be performed for obtaining one quotient. Particularly, in case of vector data constituted of a plurality of elements, the multiplying operation of the equations (1) through (2n-1) is first sequentially performed for the first element to obtain the quotient for the first element. Next, a similar multiplying operation is sequentially performed with the equations (1) through (2n-1) for the second element to obtain the quotient of the second element. For subsequent elements, similar operations are repeated for obtaining respective quotients.
In the normal vector processing system, operands are read out from a vector register at every clock cycle, and arithmetic operations, such as addition and multiplication and so forth are processed through pipeline processing. Therefore, the results of an arithmetic operation are output at every clock cycle. However, in case of the above-mentioned convergence division, multiplying operations have to be repeated many times in order to obtain the quotient for one element. It has therefore not been possible to output the result of a dividing operation at every clock cycle with the conventional vector dividing system. Also, in the conventional vector dividing system, it is not possible to read out the dividend and divisor as the operand from the vector register at every clock cycle.
As set forth above, the conventional method and system do not permit outputting the results of operation at every clock cycle and also do not permit reading out the operand at every clock cycle, since a plurality of multiplying operation iterations are required for obtaining one quotient. Therefore, this method cannot realize a high speed process employing pipeline processing.
Therefore, it is an object of the present invention to provide a vector dividing method and system which enables outputting quotients at every clock cycle while employing the pipeline processing and which can shorten the process period required for completion of arithmetic operations for all of a set of vector elements.